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ASAHI KASEI
[AK4707]
AK4707
AV SCART Switch
GENERAL DESCRIPTION The AK4707 offers the ideal features for digital set-top-box systems. The AK4707 includes the audio switches, video switches, etc. designed primarily for digital set-top-box systems. The AK4707 is offered in a space saving 48-pin LQFP package.
FEATURES Analog switches for SCART Audio section THD+N: -86dB (@2Vrms) Dynamic Range: 96dB (@2Vrms) Analog Inputs Two Full Differential Stereo Input or Single-ended input for Decoder DAC Two Stereo Input (TV & VCR SCART) Analog Outputs Two Stereo Outputs (TV & VCR SCART) Pop Noise Free Circuit for Power on/off Video section 75ohm driver 6dB Gain for Outputs Four CVBS/Y inputs (ENCx2, TV, VCR), Two CVBS/Y outputs (TV, VCR) Three R/C inputs (ENCx2, VCR), One R/C output (TV) Two G and B inputs (ENC, VCR), One G and B outputs (TV) TV/VCR input monitor Loop-through Mode for standby Auto-Startup Mode for power saving SCART pin#16 (Fast Blanking), pin#8 (Slow Blanking) Control Power supply 5V+/-5% and 12V+/-5% Low Power Dissipation / Low Power Standby Mode Package Small 48pin LQFP AK4702 Pin Compatible
MS0551-E-00 -1-
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ASAHI KASEI
[AK4707]
Block Diagram
DVCOM
-6dB to +12dB (3dB/step) AINL+ AINLAMP AINRAINR+ Volume #0 TV1-0 VD MONO TVOUTR TVOUTL
PVCOM
VCRINL VCRINR VP
TVINL
VCROUTL VCROUTR VMONO Register Control Bias VCR1-0 VSS
TVINR SCL SDA PDN
Audio Block
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ASAHI KASEI
[AK4707]
( Typical connection )
VVD1 VVD2 VVSS1 VVSS2
( Typical connection )
ENC CVBS/Y ENC Y VCR CVBS/Y TV CVBS
ENCV ENCY VCRVIN TVVIN 6dB TVVOUT
ENC R/C ENC C VCR R/C
ENCRC ENCC VCRRC 6dB TVRC TV SCART
ENC G/CVBS VCR G
ENCG VCRG 6dB TVG
ENC B VCR B
ENCB VCRB Monitor
6dB
TVB
6dB
VCRVOUT
VCR SCART
Video Block
( Typical connection ) ( Typical connection )
VCR FB
VCRFB 2V 0V TV SCART 0/ 6/ 12V TVSB 6dB TVFB
0/ 6/ 12V
Monitor
VCRSB
VCR SCART
INT
Video Blanking Block
MS0551-E-00 -3-
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ASAHI KASEI
[AK4707]
Ordering Guide
AK4707EQ -10 +70C 48pin LQFP (0.5mm pitch)
Pin Layout
VCRVOUT
AINR+
AINL+
AINR-
AINL-
TVFB
TST1
PDN
SDA
SCL
VD 38
48
47
46
45
44
43
42
41
40
39
37 36 35 34
VSS
TST2 VVSS TVVOUT VVD2 TVRC TVG TVB VVD1 ENCB ENCG ENCRC ENCC
1 2 3 4 5 6 7 8 9 10 11 12 14 17 18 23 13 15 16 19 20 21 22 24 Top View
PVCOM DVCOM VP TST4 TVOUTL TVOUTR VCROUTL VCROUTR TST3 TVINL TVINR VCRINL
AK4707EQ
33 32 31 30 29 28 27 26 25
VCRVIN
VCRSB
TVVIN
VCRG
ENCV
VCRB
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INT
VCRINR
VCRRC
VCRFB
ENCY
TVSB
2006/10
ASAHI KASEI
[AK4707]
Main difference between AK4702 and AK4707 Items Audio DAC MONO input/ output Video RGB video gain control TV/VCR video input monitor VCR Slow Blanking monitor in output mode. TV/VCR CVBS input detection & Power Save Mode RF modulator output VCR Y output
Bi-Directional Control for VCR-Red/Chroma
Pinout
Others
Pin#1 PIN#28 PIN#33 Pin #39 ~ #42 Pin#46 I2C speed (max) Mask bits for INT function (09H) FB/SB loop back in auto mode.
AK4702 AK4707 X X X X Enabled Disabled X X X X VCRC TST2 MONOIN NC MONOOUT NC I/F for DAC AMP input RFV TST1 100kHz 400kHz X X -: NOT available. X: Available
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ASAHI KASEI
[AK4707]
PIN/FUNCTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pin Name TST2 VVSS TVVOUT VVD2 TVRC TVG TVB VVD1 ENCB ENCG ENCRC ENCC ENCV ENCY TVVIN VCRVIN VCRFB VCRRC VCRG VCRB INT VCRSB TVSB VCRINR VCRINL TVINR TVINL TST3 VCROUTR VCROUTL TVOUTR TVOUTL TST4 VP I/O I O O O O I I I I I I I I I I I I O I/O O I I I I O O O O Function Test Mode Input Pin #2 Internal Pull Down 100k Normally connected to VSS. Video Ground Pin , 0V Composite/Luminance Output Pin for TV Video Power Supply Pin #2: 5V Normally connected to VVSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. Red/Chrominance Output Pin for TV Green Output Pin for TV Blue Output Pin for TV Video Power Supply Pin #1: 5V Normally connected to VVSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. Blue Input Pin for Encoder Green Input Pin for Encoder Red/Chrominance Input Pin #1 for Encoder Chrominance Input Pin #2 for Encoder Composite/Luminance Input Pin #1 for Encoder Composite/Luminance Input Pin #2 for Encoder Composite/Luminance Input Pin for TV Composite/Luminance Input Pin for VCR Fast Blanking Input Pin for VCR Red/Chrominance Input Pin for VCR Green Input Pin for VCR Blue Input Pin for VCR Interrupt Pin for Video Blanking Slow Blanking Input/Output Pin for VCR Slow Blanking Output Pin for TV Rch VCR Audio Input Pin Lch VCR Audio Input Pin Rch TV Audio Input Pin Lch TV Audio Input Pin Test Mode Input Pin #3 This pin should be connected to VSS. Rch Analog Output Pin #1 Lch Analog Output Pin #1 Rch Analog Output Pin #2 Lch Analog Output Pin #2 Test Mode Input Pin #4 This pin should be connected to VSS. Power Supply Pin, 12V Normally connected to VSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. Audio Common Voltage Pin #1 Normally connected to VSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. Audio Common Voltage Pin #2 Normally connected to VSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. The caps affect the settling time of audio bias level. Ground Pin , 0V
35
DVCOM
O
36 37
PVCOM VSS
O -
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ASAHI KASEI
[AK4707]
PIN/FUNCTION (Continued)
No. 38 39 40 41 42 43 44 45 46 47 48 Pin Name VD AINR- AINR+ AINL- AINL+ SCL SDA PDN TST1 VCRVOUT TVFB I/O I I I I I I/O I I O O Function Power Supply Pin, 5V Normally connected to VSS with a 0.1F ceramic capacitor in parallel with a 10F electrolytic cap. Rch Negative Analog Input Pin Rch Positive Analog Input Pin Lch Negative Analog Input Pin Lch Positive Analog Input Pin Control Data Clock Pin Control Data Pin Power-Down Mode Pin When at "L", the AK4707 is in the power-down mode and is held in reset. The AK4707 should always be reset upon power-up. Test Mode Input Pin #1 Internal Pull Down 100k Normally connected to VSS Composite/Luminance Output Pin for VCR Fast Blanking Output Pin for TV
Note: All digital input pins should not be left floating.
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ASAHI KASEI
[AK4707]
INTERNAL EQUIVALENT CIRCUIT
Pin No. Pin Name Type Equivalent Circuit VD
200
Description
43 45
SCL PDN
Digital IN
VSS
VD
39 40 41 42 AINRAINR+ AINL- AINL+
Audio IN
150K
VSS
VD 200
44
SDA
Digital I/O
I2C Bus voltage must not exceed VD.
VSS
VVD1
21
INT
Digital OUT
Normally connected to VD(5V) through 10k resister externally.
VSS
VVD2 VVD2
3 5 6 7 47 48
TVVOUT TVRC TVG TVB VCRVOUT TVFB
Video OUT
VVSS
VVSS
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ASAHI KASEI
[AK4707]
Pin No. 9 10 11 12 13 14 15 16 17 18 19 20
Pin Name ENCB ENCG ENCRC ENCC ENCV ENCY TVVIN VCRVIN VCRFB VCRRC VCRG VCRB
Type
Equivalent Circuit
Description
VVD1 200
Video IN
VVSS
VP 200
VP
22 23
VCRSB TVSB
Video SB
(120k) VVSS VVSS VP VVSS
The 120k is not attached for TVSB.
24 25 26 27
VCRINR VCRINL TVINR TVINL
150k
Audio IN
VSS VP VP 100
29 30 31 32
VCROUTR VCROUTL TVOUTR TVOUTL
Audio OUT
VSS VD VD
VSS VD 100
35 36
DVCOM PVCOM
VCOM OUT
VSS
VSS
VSS
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ASAHI KASEI
[AK4707]
ABSOLUTE MAXIMUM RATINGS
(VSS =VVSS = 0V; Note 1) Parameter Power Supply Symbol VD VVD1 VVD2 VP IIN VIND VINV VINA1 VINA2 Ta Tstg min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -10 -65 max 6.0 6.0 6.0 14 10 VD+0.3 VVD1+0.3 VP+0.3 VD+0.3 70 150 Units V V V V mA V V V V C C
(Note 2)
Input Current (any pins except for supplies) Input Voltage Video Input Voltage Audio Input Voltage (VCRINR/L, TVINR/L pins) Audio Input Voltage (AINL+/-, AINR+/- pins) Ambient Operating Temperature Storage Temperature
Note 1. All voltages with respect to ground. Note 2. VSS and VVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
MS0551-E-00 - 10 -
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ASAHI KASEI
[AK4707]
RECOMMENDED OPERATING CONDITIONS
(VSS = VVSS = 0V; Note 1) Parameter Power Supply (Note 3) Symbol VD VVD1 VVD2 VP min 4.75 4.75 4.75 11.4 typ 5.0 5.0 5.0 12 max 5.25 5.25 VVD1 12.6 Units V V V V
Note 1. All voltages with respect to ground. Note 3. VVD1 and VVD2 must be connected to the same voltage. *AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
ELECTRICAL CHARACTERISTICS (Ta = 25C; VP = 12V, VD = 5V; VVD1 = VVD2 = 5V) Power Supplies min Power Supply Current Normal Operation (PDN = "H") (Note 4) VD VVD1+VVD2 VP Power-Down Mode (PDN = "L") (Note 5) VD VVD1+VVD2 VP
typ
max
Units
10 20 5 10 10 10
20 40 10 100 100 100
mA mA mA A A A
Note 4. STBY bit = "0", All video outputs active. No signal, no load for A/V switches. Note 5. All digital inputs are held at VSS.
DIGITAL CHARACTERISTICS (Ta = 25C; VD = 4.75 5.25V) Parameter Symbol min High-Level Input Voltage VIH 2.0 Low-Level Input Voltage VIL Low-Level Output Voltage VOL (SDA pin: Iout= 3mA, INT pin: Iout= 1mA) Input Leakage Current Iin -
typ -
max 0.8 0.4 10
Units V V V A
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ASAHI KASEI
[AK4707]
ANALOG CHARACTERISTICS (AUDIO) (Ta = 25C; VP = 12V, VD = 5V; VVD1 = VVD2 = 5V; Signal Frequency = 1kHz; Measurement frequency = 20Hz 20kHz; RL 4.5k; 0dB=2Vrms output; unless otherwise specified) Parameter min typ max Analog Input: (TVINL/TVINR/VCRINL/VCRINR pins) Analog Input Characteristics Input Voltage 2.0 Input Resistance 100 150 Analog Input: (AINL+/AINL-/AINR-/AINR+ pins) Analog Input Characteristics Input Voltage 1.0 Input Resistance 100 150 Stereo/Mono Output: (TVOUTL/TVOUTR/VCROUTL/VCROUTR pins) (Note 6) Analog Output Characteristics Volume#0 Step Width 2.3 3.0 3.7 THD+N (at 2Vrms output) (Note 7) -80 -86 92 96 Dynamic Range (-60dB Output, A-weighted) (Note 7) S/N (A-weighted) (Note 7) 92 96 Interchannel Isolation (Note 7,Note 8) 80 90 Interchannel Gain Mismatch (Note 7,Note 0.3 8) Gain Drift 200 Load Resistance (AC-Lord, Note 10) TVOUTL/R, VCROUTL/R 4.5 Load Capacitance TVOUTL/R, VCROUTL/R 20 Output Voltage 1.85 2 2.15 Frequency Response 0 20.0kHz 0.5 Power Supply Rejection (PSR) (Note 9) 50
Note 6. Measured by Audio Precision System Two Cascade. Note 7. Analog In to TVOUT. Path : AINL+/- TVOUTL, AINR+/- TVOUTR Note 8. Between TVOUTL and TVOUTR with analog inputs AINL+/-, AINR+/-, 1kHz/0dB. Note 9. The PSR is applied to VD with 1kHz, 100mV. Note 10. THD+N: -80dB(min. at 2Vrns)
Units
Vrms k
Vrms k
dB dB dB dB dB dB ppm/C k pF Vrms dB dB
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ASAHI KASEI
[AK4707]
ANALOG CHARACTERISTICS (VIDEO) (Ta = 25C; VP = 12V, VD= 5V; VVD1 = VVD2 = 5V; unless otherwise specified.) Parameter Conditions Sync Tip Clamp Voltage at output pin. Chrominance Bias Voltage at output pin. Gain Input = 0.3Vp-p, 100kHz Interchannel Gain Mismatch TVRC, TVG, TVB. Input = 0.3Vp-p, 100kHz. Frequency Response Input=0.3Vp-p, 100kHz to 6MHz Input Impedance Chrominance input (internally biased) Input Signal f = 100kHz, maximum with distortion < 1.0% Load Resistance (Note 11) Load Capacitance C1 (Note 11) C2 (Note 11) Dynamic Output Signal f = 100kHz, maximum with distortion < 1.0% Y/C Crosstalk f = 4.43MHz, 1Vp-p input. Among TVVOUT, TVRC and VCRVOUT outputs. S/N Reference Level = 0.7Vp-p, CCIR 567 weighting. BW = 15kHz to 5MHz. Differential Gain 0.7Vpp 5steps modulated staircase. chrominance &burst are 280mVpp, 4.43MHz. Differential Phase 0.7Vpp 5steps modulated staircase. chrominance &burst are 280mVpp, 4.43MHz.
Note 11. Refer the Figure 1.
R1 75 ohm Video Signal Output C2 max: 15pF C1 max: 400pF
min
5.5 -0.5 -1.0 40 150
typ 0.7 2.2 6 60 -
max
-
-50 74 0.3 0.3
6.5 0.5 1.0 1.5 400 15 3 -
Units V V dB dB dB k Vpp pF pF Vpp dB dB % Degree
R2 75 ohm
Figure 1. Load Resistance R1+R2 and Load Capacitance C1/C2.
MS0551-E-00 - 13 -
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ASAHI KASEI
[AK4707]
SWITCHING CHARACTERISTICS (Ta = 25C; VP = 11.4 12.6V, VD = 4.75 5.25V, VVD1 = VVD2 = 4.75 5.25V) Parameter Symbol min typ Control Interface Timing (I2C Bus): SCL Clock Frequency fSCL Bus Free Time Between Transmissions tBUF 1.3 Start Condition Hold Time tHD:STA 0.6 (prior to first clock pulse) Clock Low Time tLOW 1.3 Clock High Time tHIGH 0.6 Setup Time for Repeated Start Condition tSU:STA 0.6 SDA Hold Time from SCL Falling (Note 12) tHD:DAT 0 SDA Setup Time from SCL Rising tSU:DAT 0.1 Rise Time of Both SDA and SCL Lines tR Fall Time of Both SDA and SCL Lines tF Setup Time for Stop Condition tSU:STO 0.6 Pulse Width of Spike Noise tSP 0 Suppressed by Input Filter Capacitive load on bus Cb Reset Timing tPD 150 PDN Pulse Width (Note 13)
Note 12. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 13. The AK4707 should be reset by PDN pin = "L" upon power up. Note 14. I2C is a registered trademark of Philips Semiconductors.
max 400 0.3 0.3 50 400
Units kHz s s s s s s s s s s ns pF ns
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ASAHI KASEI
[AK4707]
Timing Diagram
VIH SDA VIL tBUF SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA Start
I2C Bus mode Timing
tPD
tLOW
tR
tHIGH
tF
tSP VIH
tSU:STO Stop
PDN
VIL
Power-down Timing
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ASAHI KASEI
[AK4707]
OPERATION OVERVIEW
1. System Reset and Power-down options
The AK4707 should be reset once by bringing PDN pin = "L" upon power-up. The AK4707 has several operation modes. The PDN pin, AUTO bit, BIAS bit, STBY bit and AMP bit control operation modes as shown in Table 1 and Table 2. Mode 0 1 2 3 4 5 PDN pin "L" "H" "H" "H" "H" "H" Mode Full Power-down Auto Startup mode 1 * * (Power-on default) 0 1 1 Standby & Mute 0 1 0 Standby Mute 0 0 1 (AMP power down) Normal operation 0 0 0 (AMP operation) Table 1. Operation Mode Settings (*: Don't Care) Register Control Not available No video input Video input (2) Available Audio Bias Level Power down Video Output Hi-Z TVFB, TVSB Hi-Z VCRSB AUTO bit * STBY bit * BIAS bit *
Mode 0 Full Power-down Auto Startup mode (Power-on default) Standby & Mute Standby Mute (AMP power down) Normal operation (AMP operation)
Pull-down (1)
1
Active Power down Active Power down Active (3)
Active
2 3 4 5
Active Hi-Z / Active
Active
Note 15. Internally pulled down by 120k (typ) resistor. Note 16. Video input to TVVIN or VCRVIN. Note 17. TVOUTL/R are muted by Mute bit in the default state. Table 2. Status of each operation modes
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ASAHI KASEI
[AK4707]
Full Power-down Mode
The AK4707 should be reset once by bringing PDN pin = "L" upon power-up. PDN pin: Power down pin L: Device power down. H: Normal operation.
Auto Startup Mode
After when the PDN pin is set to "H", the AK4707 is in the auto startup mode. In this mode, all blocks except for the video detection circuit are powered down. Once the video detection circuit detects video signal from TVVIN pin or VCRVIN pin, the AK4707 goes to the stand-by mode automatically and sends "H" pulse via INT pin. The sources of TVOUTL/R are fixed to VCRINL/R, the sources of VCROUTL/R are fixed to TVINL/R respectively. The source of DC- restore circuit is VCRVIN pin. To exit the auto startup mode, set the AUTO bit to "0". AUTO bit (00H D3): Auto startup bit 0: Auto startup disable. (Manual startup) 1: Auto startup enable. (default)
Bias Mode
When the BIAS bit = "1", the bias voltage on the audio output goes to GND level. Bringing BIAS bit to "0" changes this bias voltage smoothly from GND to VP/2 by 2sec (typ.). This removes the huge click noise related the sudden change of bias voltage at power-on. The change of BIAS bit from "1" to "0" also makes smooth transient from VP/2 to GND by 2sec (typ). This removes the huge click noise related the sudden change of bias voltage at power-off. BIAS bit (00H D1): Bias-off bit 0: Normal operation. 1: Set the audio bias to GND. (default)
Standby Mode
When the AUTO bit = BIAS bit = "0" and the STBY bit = "1", the AK4707 is forced into TV-VCR loop through mode. In this mode, the sources of TVOUTL/R pins are fixed to VCRINL/R pins; the sources of VCROUTL/R are fixed to TVINL/R pins respectively. All register values themselves are NOT changed by STBY bit = "1". STBY bit (00H D0): Standby bit 0: Normal operation. 1: Standby mode. (default)
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ASAHI KASEI
[AK4707]
Normal Operation Mode
To change analog switches, set the AUTO bit, BIAS bit and STBY bit to "0". The AK4707 is in power-down mode until PDN pin = "H". The Figure 2 shows an example of the system timing at the power-down and power-up by PDN pin.
Typical Operation Sequence (auto setup mode)
Figure 2 shows an example of the system timing at auto setup mode.
PDN pin TVVIN VCRVIN TVVOUT, VCRVOUT Audio out (DC)
Low Power Mode
Low Power Mode
Low Power Mode
don't care
No Signal
Signal in
No Signal
Signal in
No Signal
don't care
don't care
No Signal
Signal in
No Signal
don't care
Hi-Z
Active (loop-through)
Hi-Z
Active (loop-through)
Hi-Z
(GND)
Active (loop-through)
Active (loop-through)
Figure 2. Typical operating sequence (auto setup mode)
Typical Operation Sequence (except auto setup mode)
Figure 3 shows an example of the system timing at auto setup mode.
PDN pin AUTO bit BIAS bit STBY bit TV-Source select "1" (default) "1" (default) "1" (default)
"Stand-by"
"Mute"
"Stand-by"
"0" "0" "1" "0" "0" "1" "1"
fixed to VCR in(Loop-through)
VCR in (default)
AMP
VCR in
fixed to VCR in(Loop-through)
TV out
VCR in
AMP
AMP
VCR in
(1)
(2)
Notes: (1) Set the STBY bit = "0" to pass for 20.2ms after set the MUTE bit = "0", to prevent the click noise (1). (2) Mute the analog outputs externally if click noise (2) affects the system. Figure 3. Typical operating sequence (except auto setup mode)
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ASAHI KASEI
[AK4707]
2. Audio Block
Switch Control
The AK4707 has switch matrixes designed primarily for SCART routing. Those are controlled via the control register as shown in, Table 3 and Table 4 (Please refer to the Block Diagram). (01H: D1-D0) TV1 TV0 Source of TVOUTL/R 0 0 AMP 0 1 VCRIN (default) 1 0 Mute 1 1 (Reserved) Table 3. TVOUT Switch Configuration (01H: D5-D4) VCR1 VCR0 Source of VCROUTL/R 0 0 AMP 0 1 TVIN (default) 1 0 Mute 1 1 (Reserved) Table 4. VCROUT Switch Configuration
Volume Control #0 (7-Level Volume)
The AK4707 has a 7-level volume control (Volume #0) as shown in Table 5. The volume reflects the change of register value immediately.
1Vrms 2Vrms differential input 1Vrms
AINL/R+
0.47 0.47
2Vrms Volume Gain 0dB TVOUTL/R Volume #0 (VCROUTL/R)
AINL/R-
Figure 4. Volume #0(Volume Gain=0dB:default), Full Differential Stereo Input (02H: D5-D3) L2 L1 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0
L0 Volume #0 Gain Output Level (Typ) 1 +12dB 2Vrms (with 0.5Vrms differential input) 0 +9dB 1 +6dB 2Vrms (with 1Vrms differential input) 0 +3dB 1 0dB 2Vrms (with 2Vrms differential input: default) 0 -3dB 1 -6dB 1Vrms (with 2Vrms differential input) 0 Mute Table 5. Volume #0, Full Differential Stereo Input
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ASAHI KASEI
[AK4707]
1Vrms
1Vrms AINL/R+
0.47
Volume Gain 0dB TVOUTL/R Volume #0 (VCROUTL/R)
AINL/R0.47
Figure 5. Volume #0(Volume Gain=0dB:default), Single-ended Input (02H: D5-D3) VOL2 VOL1 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 0
VOL0 1 0 1 0 1 0 1 0
Volume #0 Gain +12dB +9dB +6dB +3dB 0dB -3dB -6dB Mute
Output Level (Typ) 2Vrms (with 0.5Vrms input) 2Vrms (with 1Vrms input) 1Vrms (with 1Vrms input: default) 0.5Vrms (with 1Vrms input) -
Table 6. Volume #0, Single-ended Input
MUTE Control
To minimize the click noise at setting the MUTE bit = "1", the AK4707 has a zero-cross detection. When the ZERO bit = "1", the zero-cross detection function is enabled. TVOUTL/R outputs analog common voltage at the input signal first zero-cross point from setting the MUTE bit = "1" or when the zero-cross is not detected within the time set by ZTM1-0 bits (12.8msec to 102.4msec). TVOUTL/R outputs of TV1-0 switch at the input signal first zero-cross point from setting the MUTE bit = "0" or when the zero-cross is not detected within the time set by ZTM1-0 bits. The zero-cross is detected on L/R channels at the TV1/0 selector independently. To disable this function, set the ZERO bit to "0". ZERO: Zero-cross detection enable for TV1/0 selector 0: Disable 1: Enable (default)
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ASAHI KASEI
[AK4707]
3. Video Block
Video Switch Control
The AK4707 has switches for TV and VCR. Each switch can be controlled via registers independently. When AUTO bit = "1" or STBY bit = "1", these switches setting is ignored and set to fixed configuration (loop-through mode). Refer the auto setup mode and standby mode. (04H: D2-D0) Mode Shutdown Encoder CVBS /RGB Encoder Y/C 1 Encoder Y/C 2 VCR (default) TV CVBS (Reserved) (Reserved) VTV2-0 bit 000 001 010 011 100 101 110 111 Source of Source of Source of TVVOUT pin TVRC pin TVG pin (Hi-Z) (Hi-Z) (Hi-Z) ENCV pin ENCRC pin ENCG pin (Encoder CVBS) (Encoder Red,C) (Encoder Green) ENCV pin ENCRC pin Hi-Z (Encoder Y) (Encoder C) ENCY pin ENCC pin Hi-Z (Encoder Y) (Encoder C) VCRVIN pin VCRG pin VCRRC (VCR CVBS) (VCR Green) (VCR Red,C) TVVIN pin (Hi-Z) (Hi-Z) (TV CVBS) Table 7. TV video output (Refer Note 18.) Source of TVB pin (Hi-Z) ENCB pin (Encoder Blue) (Hi-Z) (Hi-Z) VCRB pin (VCR Blue) (Hi-Z) -
(04H: D5-D3) Source of VCRVOUT pin Shutdown 000 (Hi-Z) ENCV pin Encoder CVBS or Y/C 1 001 (Encoder CVBS) ENCY pin Encoder CVBS or Y/C 2 010 (Encoder CVBS) TVVIN pin TV CVBS (default) 011 (TV CVBS) VCRVIN pin VCR 100 (VCR CVBS) (Reserved) 101 (Reserved) 110 (Reserved) 111 Table 8. VCR video output (Refer Note 18.) Mode VVCR2-0 bit Note 18. When input the video signal via ENCRC pin or VCRRC pin, set CLAMP1-0 bits respectively.
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ASAHI KASEI
[AK4707]
Video Output Control (05H: D6-D0)
Each video output can be set to Hi-Z individually via control registers. These settings are ignored when the AUTO bit = "1". TVV: TVVOUT output control TVR: TVRCOUT output control TVG: TVGOUT output control TVB: TVBOUT output control VCRV: VCRVOUT output control TVFB: TVFB output control 0: Hi-Z. (default) 1: Active.
Clamp and DC-restore circuit control (06H: D6-D5, D3-D2)
Each CVBS and Y input has the sync tip clamp circuit. The sync tip voltage at each output is 0.7V (typ). This corresponds 0.35V (typ) at the SCART connector when matched by 75 resistors. The CLAMP1-0 bits select the input circuit for ENCRC pin (Encoder Red/Chroma) and VCRRC pin (VCR Red/Chroma) respectively. VCLP1-0 bits select the source of DC-restore circuit. CLAMP1: Encoder Red/Chroma (ENCRC pin) input clamp control 0: DC restore clamp active (for RED signal. default) 1: Biased (for Chroma signal) CLAMP0: VCR R/C (VCRRC pin) input clamp control 0: DC restore clamp active (for RED signal) 1: Biased (for Chroma signal. default) VCLP1-0: DC restore source control When the AUTO bit = "1", the source is fixed to VCRVIN. VCLP1 bit VCLP0 bit Sync Source of DC Restore 0 0 ENCV (default) 0 1 ENCY 1 0 VCRVIN 1 1 (Reserved) Table 9. DC restore source control
MS0551-E-00 - 22 -
2006/10
ASAHI KASEI
[AK4707]
4. Blanking Control
The AK4707 supports Fast Blanking signals and Slow Blanking (Function Switching) signals for TV/VCR SCART.
Input/Output Control for Fast/Slow Blanking
FB1-0: TV Fast Blanking output control (07H: D1-D0) FB1 bit FB0 bit TVFB pin Output Level 0 0 0V (default) 0 1 2V<, 4V(typ) at 150 load 1 0 Same as VCR FB input (4V/0V) 1 1 (Reserved) Table 10. TV Fast Blanking output (Note: minimum load is 150) SBT1-0: TV Slow Blanking output control (07H: D3-D2) SBT1 bit SBT0 bit TVSB pin Output Level 0 0 < 2V (default) 0 1 5V <, < 7V 1 0 (Reserved) 1 1 10V < Table 11. TV Slow Blanking output (Note: minimum load is 10k) SBV1-0: VCR Slow Blanking output control (07H: D5-D4) SBV1 bit SBV0 bit VCRSB pin Output Level 0 0 < 2V (default) 0 1 5V <, < 7V 1 0 (Reserved) 1 1 10V < Table 12. VCR Slow Blanking output (Note: minimum load is 10k) SBIO1-0: TV/VCR Slow Blanking I/O control (07H: D7-D6) SBIO1 bit 0 0 1 1 SBIO0 bit 0 1 0 1 VCRSB pin Direction TVSB pin Direction Output Output (Controlled by SBV1-0 bits) (Controlled by SBT1-0 bits) (Reserved) (Reserved) Input Output (Stored in SVCR1-0 bits) (Controlled by SBT1-0 bits) Input Output (Stored in SVCR1-0 bits) (Same output as VCR SB) Table 13. TV/VCR Slow Blanking I/O control
(default)
MS0551-E-00 - 23 -
2006/10
ASAHI KASEI
[AK4707]
5. Monitor Options and INT function
Monitor Options (08H: D4-D0)
The AK4707 has several detection functions. SVCR1-0 bits, FVCR bit, VCMON bit and TVMON bit reflect the input DC level of VCR slow blanking, the input DC level of VCR fast blanking and signals input to TVVIN or VCRVIN pins. SVCR1-0: VCR Slow blanking status monitor SVCR1-0 bits reflect the voltage at VCRSB pin only when the VCRSB is in the input mode. When the VCRSB is in the output mode, SVCR1-0 bits hold previous value. VCRSB pin input level SVCR1 bit SVCR0 bit < 2V 0 0 4.5V to 7V 0 1 (Reserved) 1 0 9.5V < 1 1 Table 14. VCR Slow Blanking monitor FVCR: VCR Fast blanking input level monitor This bit is enabled when TVFB bit = "1". VCRFB pin input level FVCR bit < 0.4V 0 1V < 1 Table 15. VCR Fast Blanking monitor (Typical threshold is 0.7V)
VCMON: VCRVIN pin video input monitor (MCOMN bit = "1"), TVVIN pin or VCRVIN pin video input monitor (MCOMN bit = "0") 0: No video signal detected. 1: Detects video signal. TVMON: TVVIN pin video input monitor (active when MCOMN bit = "1") 0: No video signal detected. 1: Detects video signal.
AUTO (00H D3) 0 0 0 0 0 0 0 0 1 1 1 1 MCOMN (09H D7) 0 0 0 0 1 1 1 1 * * * * TVVIN signal 0 0 1 1 0 0 1 1 0 0 1 1 VCRVIN signal 0 1 0 1 0 1 0 1 0 1 0 1 TVMON (08H D4) 0 0 0 0 0 0 1 1 0 0 0 0 VCMON (08H D3) 0 1 1 1 0 1 0 1 0 1 1 1
*:don't care, Note 19. TVVIN/VCRVIN signal: signal 0 = No signal applied, signal 1 = signal applied Table 16. TV/VCR Monitor Function
MS0551-E-00 - 24 -
2006/10
ASAHI KASEI
[AK4707]
INT Function and Mask Options (09H: D3-D1)
Changes of the 08H status can be monitored via the INT pin. The INT pin is the open drain output and goes "L" for 2s (typ.) when the status of 08H is changed. This pin should be connected to VD (typ. 5V) through 10kohm resistor. MTV bit, MVC bit, MCOMN bit, MFVCR bit and MSVCR bit control the reflection of the status change of these monitors onto the INT pin from report to prevent to masks each monitor.
AK4707
VD R=10k INT uP
Figure 6. INT pin MVC: VCMON Mask. Refer Table 18 MTV: TVMON Mask. Refer Table 17 MCOMN: Refer Table 16 AUTO (00H D3) 0 0 0 0 TVMON MTV INT (08H D4) (09H D4) No Change 0 Hi-Z No Change 1 Hi-Z Change 0 Generates "L" Pulse Change 1 Hi-Z No Change 0 Hi-Z 1 1 No Change 1 Hi-Z Note 20. When the STBY bit = "0", the TV Monitor Mask function is enabled. Note 21. When AUTO bit = "1", TVMON does not change. Table 17. TV Monitor Mask VCMON (08H D3) No Change No Change Change Change MVC (09H D3) 0 1 0 1 INT Hi-Z Hi-Z Generates "L" Pulse Hi-Z
AUTO (00H D3) 0 0 0 0
1 No Change 0 Hi-Z 1 No Change 1 Hi-Z 1 Change 0 Generates "L" Pulse 1 Change 1 Generates "L" Pulse Note 22. When the STBY bit = "0", the VCR Monitor Mask function is enabled. Table 18. VCR Monitor Mask MFVCR: FVCR Monitor mask. 0: Change of FVCR is reflected to INT pin. (default) 1: Change of FVCR is NOT reflected to INT pin. MSVCR: SVCR1-0 Monitor mask 0: Change of SVCR1-0 is reflected to INT pin. (default) 1: Change of SVCR1-0 is NOT reflected to INT pin.
MS0551-E-00 - 25 -
2006/10
ASAHI KASEI
[AK4707]
6. Control Interface
I2C-bus Control Mode 1. WRITE Operations Figure 7 shows the data transfer sequence in I2C-bus mode. All commands are preceded by a START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 13). After the START condition, a slave address is sent. This address is 7bits long followed by an eighth bit that is a data direction bit (R/W). The most significant seven bits of the slave address are fixed as "0010001". If the slave address match that of the AK4707, the AK4707 generates the acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 15). A "1" for R/W bit indicates that the read operation is to be executed. A "0" indicates that the write operation is to be executed. The second byte consists of the address for control registers of the AK4707. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 9). The data after the second byte contain control data. The format is MSB first, 8bits (Figure 10). The AK4707 generates an acknowledge after each byte has been received. A data transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 13). The AK4707 can execute multiple one byte write operations in a sequence. After receipt of the third byte, the AK4707 generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 09H prior to generating the stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW (Figure 15) except for the START and the STOP condition.
S T A R T S T O P Data(n) A C K A C K Data(n+1) A C K A C K Data(n+x) A C K P
R/W= "0"
SDA
S
Slave Address A C K
Sub Address(n)
Figure 7. Data transfer sequence at the I2C-bus mode
0
0
1
0
0
0
1
R/W
Figure 8. The first byte
0
0
0
A4
A3
A2
A1
A0
Figure 9. The second byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 10. Byte structure after the second byte
MS0551-E-00 - 26 -
2006/10
ASAHI KASEI
[AK4707]
2. READ Operations Set R/W bit = "1" for READ operations. After transmission of data, the master can read the next address's data by generating an acknowledge instead of terminating the write cycle after the receipt the first data word. After the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 09H prior to generating the stop condition, the address counter will "roll over" to 00H and the previous data will be overwritten. The AK4707 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ. 2-1. CURRENT ADDRESS READ The AK4707 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next CURRENT READ operation would access data from the address n+1. After receipt of the slave address with R/W bit set to "1", the AK4707 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4707 discontinues transmission.
S T A R T R/W= "1" S T O P Data(n+1) A C K A C K Data(n+2) A C K A C K Data(n+x) A C K P
SDA
S
Slave Address A C K
Data(n)
Figure 11. CURRENT ADDRESS READ 2-2. RANDOM READ Random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. The master issues a start condition, slave address (R/W bit = "0") and then the register address to read. After the register's address is acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to "1". Then the AK4707 generates an acknowledge, 1-byte data and increments the internal address counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4707 discontinues transmission.
S T A R T S T A R T S A C K Slave Address A C K S T O P Data(n+1) A C K A C K A C K Data(n+x) A C K P
R/W= "0"
R/W= "1"
SDA
S
Slave Address A C K
Sub Address(n)
Data(n)
Figure 12. RANDOM ADDRESS READ
MS0551-E-00 - 27 -
2006/10
ASAHI KASEI
[AK4707]
SDA
SCL S start condition P stop condition
Figure 13. START and STOP conditions
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S clock pulse for acknowledgement
1
2
8
9
START CONDITION
Figure 14. Acknowledge on the I2C-bus
SDA
SCL
data line stable; data valid
change of data allowed
Figure 15. Bit transfer on the I2C-bus
MS0551-E-00 - 28 -
2006/10
ASAHI KASEI
[AK4707]
Register Map
Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H Register Name Control Switch Main Volume Zerocross Video switch Video output enable Video clamp S/F Blanking control S/F Blanking monitor Monitor mask D7 0 MUTE 0 0 0 0 0 SBIO1 0 MCOMN D6 0 0 0 VMONO 0 TVFB VCLP1 SBIO0 0 0 D5 0 VCR1 L2 0 VVCR2 0 VCLP0 SBV1 0 0 D4 0 VCR0 L1 0 VVCR1 VCRV 0 SBV0 TVMON MTV D3 AUTO MONO L0 0 VVCR0 TVB CLAMP1 SBT1 VCMON MVC D2 0 0 1 ZERO VTV2 TVG CLAMP0 SBT0 FVCR MFVCR D1 BIAS TV1 1 ZTM1 VTV1 TVR 0 FB1 SVCR1 MSVCR D0 STBY TV0 1 ZTM0 VTV0 TVV 0 FB0 SVCR0 0
When the PDN pin goes "L", the registers are initialized to their default values. While the PDN pin = "H", all registers can be accessed. Do not write any data to the register over 09H.
Register Definitions
Addr 00H Register Name Control R/W Default D7 0 0 D6 0 0 D5 0 0 D4 0 R/W 0 1 0 1 1 D3 AUTO D2 0 D1 BIAS D0 STBY
STBY: Standby control 0: Normal Operation 1: Standby Mode (default). All registers are not initialized. Source of TVOUT : fixed to VCRIN, Source of VCROUT : fixed to TVIN Source of TVVOUT : fixed to VCRVIN (or Hi-Z), Source of TVRC : fixed to VCRRC (or Hi-Z), Source of TVG : fixed to VCRG (or Hi-Z), Source of TVB : fixed to VCRB (or Hi-Z), Source of VCRVOUT : fixed to TVVIN (or Hi-Z), Source of TVFB : fixed to VCRFB (or Hi-Z), Source of TVSB : fixed to VCRSB.
BIAS: Audio output control 0: Normal operation 1: ALL Audio outputs to GND (default) AUTO: Auto startup bit 0: Auto startup disable (Manual startup). 1: Auto startup enable (default). Note 23. When the SBIO1 bit = "1"(default = "0"), the change of AUTO bit may cause a "L" pulse on INT pin.
MS0551-E-00 - 29 -
2006/10
ASAHI KASEI
[AK4707]
Addr 01H
Register Name Switch R/W Default
D7 MUTE 1
D6 0 0
D5 VCR1 0
D4 VCR0 1
D3 MONO R/W 0
D2 1 1
D1 TV1 0
D0 TV0 1
TV1-0: TVOUTL/R pins source switch 00: AMP 01: VCRINL/R pins (default) 10: MUTE 11: Reserved MONO: Mono select for TVOUTL/R pins 0: Stereo. (default) 1: Mono. (L+R)/2 VCR1-0: VCROUTL/R pins source switch 00: AMP 01: TVINL/R pins (default) 10: MUTE 11: Reserved MUTE: Mute switch 0: Normal operation 1: Mute (default) When Mute bit = "1", TVOUTL/R outputs VCOM voltage after TVOUTL/R output is zero-crossing (ZERO bit= "1"). Set the MUTE bit= "1" to pass for 100ms after setting the PDN pin="H".
Addr 02H
Register Name Main volume R/W Default
D7 0 0
D6 0 0
D5 L2 0
D4 L1 R/W 1
D3 L0 1
D2 1 1
D1 1 1
D0 1 1
L2-0: Volume #0 control Those registers control both Lch and Rch of Volume #0. 111: Volume gain = +12dB 110: Volume gain = +9dB 101: Volume gain = +6dB 100: Volume gain = +3dB 011: Volume gain = +0dB (default) 010: Volume gain = -3dB 001: Volume gain = -6dB 000: MUTE
MS0551-E-00 - 30 -
2006/10
ASAHI KASEI
[AK4707]
Addr 03H
Register Name Zerocross R/W Default
D7 0 0
D6
VMONO 0
D5 0 0
D4 0 R/W 0
D3 0 0
D2 ZERO 1
D1 ZTM1 0
D0 ZTM0 0
ZTM1-0: The time length control of zero-cross timeout 00: typ. 12.8ms, max. 20.2ms (default) 01: typ. 25.6ms 10: typ. 51.2ms 11: typ. 102.4ms ZERO: Zero-cross detection enable for TVOUT output 0: Disable The TVOUTL/R outputs VCOM voltage immediately without zero-cross when MUTE bit = "1". The TVOUTL/R outputs of TV1-0 switch immediately without zero-cross when MUTE bit = "0". 1: Enable (default) The TVOUTL/R outputs VCOM voltage when timeout or zero-cross before timeout when MUTE bit = "1". The TVOUTL/R outputs of TV1-0 switch when timeout or zero-cross before timeout when MUTE bit = "0". VMONO: Mono select for VCROUTL/R pins 0: Stereo. (default) 1: Mono. (L+R)/2
MS0551-E-00 - 31 -
2006/10
ASAHI KASEI
[AK4707]
Addr 04H
Register Name Video switch R/W Default
D7 0 0
D6 0 0
D5 VVCR2 0
D4 D3 VVCR1 VVCR0 R/W 1 1
D2 VTV2 1
D1 VTV1 0
D0 VTV0 0
VTV2-0: Selector for TV video output Refer the Table 7. VVCR2-0: Selector for VCR video output Refer the Table 8.
Addr 05H
Register Name Output Enable R/W Default
D7 0 0
D6 TVFB 0
D5 0 0
D4 D3 VCRV TVB R/W 0 0
D2 TVG 0
D1 TVR 0
D0 TVV 0
TVV: TVVOUT output control TVR: TVRCOUT output control TVG: TVGOUT output control TVB: TVBOUT output control VCRV: VCRVOUT output control TVFB: TVFB output control 0: Hi-Z (default) 1: Active.
MS0551-E-00 - 32 -
2006/10
ASAHI KASEI
[AK4707]
Addr 06H
Register Name Video Clamp R/W Default
D7 0 0
D6 VCLP1 0
D5 VCLP0 0
D4 0
D3 CLAMP1 R/W 0 0
D2 CLAMP0 1
D1 0 0
D0 0 0
CLAMP1: Encoder R/Chroma (ENCRC pin) input clamp control 0: DC restore clamp active (for RED signal. default) 1: Biased (for Chroma signal.) CLAMP0: VCR R/C (VCRC pin) input clamp control 0: DC restore clamp active (for RED signal) 1: Biased (for Chroma signal. default.) VCLP1-0: DC restore source control 00: ENCV pin (default) 01: ENCY pin 10: VCRVIN pin 11: (Reserved) When the AUTO bit = "1", the source is fixed to VCRVIN pin.
Addr 07H
Register Name S/F Blanking R/W Default
D7 SBIO1 0
D6 SBIO0 0
D5 SBV1 0
D4 D3 SBV0 SBT1 R/W 0 0
D2 SBT0 0
D1 FB1 0
D0 FB0 0
FB1-0: TV Fast Blanking output control (for TVFB pin) 00: 0V (default) 01: 2V<, 4V(typ.) at 150 load 10: follow VCR FB input (4V/0V) 11: (Reserved) SBT1-0: TV Slow Blanking output control (for TVSB pin. minimum load is 10k.) 00: < 2V (default) 01: 5V <, < 7V 10: (Reserved) 11: 10V < SBV1-0: VCR Slow Blanking output control (for VCRSB pin. minimum load is 10k.) 00: < 2V (default) 01: 5V <, < 7V 10: (Reserved) 11: 10V < SBIO1-0: TV/VCR Slow Blanking I/O control Refer the Table 13.
MS0551-E-00 - 33 -
2006/10
ASAHI KASEI
[AK4707]
Addr 08H
Register Name SB/FB monitor R/W Default
D7 0 0
D6 0 0
D5 0 0
D4 D3 TVMON VCMON READ 0 0
D2 FVCR 0
D1 SVCR1 0
D0 SVCR0 0
SVCR1-0: VCR Slow blanking status monitor SVCR1-0 bits reflect the voltage at VCRSB pin only when the VCRSB is in the input mode. When the VCRSB is in the output mode, SVCR1-0 bits hold previous value. VCRSB pin input level SVCR1 bit SVCR0 bit < 2V 0 0 4.5V to 7V 0 1 (Reserved) 1 0 9.5V < 1 1 Table 19. VCR Slow Blanking monitor FVCR: VCR Fast blanking input level monitor This bit is enabled when TVFB bit = "1". VCRFB pin input level FVCR bit < 0.4V 0 1V < 1 Table 20. VCR Fast Blanking monitor (Typical threshold is 0.7V) VCMON: TVMON: Refer the Table 16.
Addr 09H
Register Name Monitor mask R/W Default
D7 MCOMN 0
D6 0 0
D5 0 0
D4 MTV 0
D3 MVC R/W 1
D2 MFVCR 0
D1 MSVCR 0
D0 0 0
MSVCR: SVCR1-0 bits Monitor mask 0: The INT pin reflects the change of SVCR1-0 bit. (default) 1: The INT pin does not reflect the change of SVCR1-0 bits. MFVCR: FVCR Monitor mask 0: The INT pin reflects the change of FVCR bit. (default) 1: The INT pin does not reflect the change of FVCR bit. MVC: VCR input monitor mask Refer the Table 18. MTV: TV input monitor mask Refer the Table 17. MCOMN: Monitor mask option Refer the Table 16.
MS0551-E-00 - 34 -
2006/10
ASAHI KASEI
[AK4707]
SYSTEM DESIGN
Figure 16 and Figure 17 shows the system connection diagram example. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results.
Audio 5V
75
75
0.47u
0.47u
0.47u
0.47u
+ 10u 0.1u VSS 37 VD 38
VCRVOUT 47
TST1 46
PDN 45
SDA 44
SCL 43
AINL+ 42
AINL- 41
AINR+ 40
AINR- 39
TVFB 48
0.1u
10u + 10u
0.1u
10u 0.1u 10u 0.1u 75 + +
2 VVSS 3 TVVOUT 4 VVD2
DVCOM 35 VP 34 TST4 33
+ 0.1u
10u +
1 TST2
PVCOM 36
Analog 12V
300
75 75 75
5 TVRC 6 TVG 7 TVB 8 VVD1 75 0.1u 0.1u 0.1u 0.1u 9 ENCB 10 ENCG 11 ENCRC 16 VCRVIN 75 75 75
AK4707EQ
TVOUTL 32 TVOUTR 31 VCROUTL 30 VCROUTR 29 TST3 28 TVINL TVINR 23 TVSB 24 VCRINR 27 26
+ 10u + 10u + 10u + 10u
220k 220k 220k 220k 0.47u 0.47u 0.47u
300 300 300
Video 5V
controller
300 300 300
18 VCRRC
DACL DACR
MPEG decoder
22 VCRSB
17 VCRFB
12 ENCC 15 TVVIN 13 ENCV 14 ENCY
19 VCRG
VCRINL 25
20 VCRB
21 INT
Digital Ground
Analog Ground
Figure 16. Typical Connection Diagram (Full Differential Stereo Input)
MS0551-E-00 - 35 -
75
VCR SCART
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
encoder
VIDEO
75
75
75
75
75
75
75
0.47u
400
400
300
TV SCART
Micro
2006/10
ASAHI KASEI
[AK4707]
Audio 5V
75
75
0.47u
0.47u
0.47u
0.47u
+ 10u 0.1u VSS 37 VD 38
VCRVOUT 47
TST1 46
PDN 45
SDA 44
SCL 43
AINL+ 42
AINL- 41
AINR+ 40
AINR- 39
TVFB 48
0.1u
10u + 10u
0.1u
10u 0.1u 10u 0.1u 75 + +
2 VVSS 3 TVVOUT 4 VVD2
DVCOM 35 VP 34 TST4 33
+ 0.1u
10u +
1 TST2
PVCOM 36
Analog 12V
300
75 75 75
5 TVRC 6 TVG 7 TVB 8 VVD1 75 0.1u 0.1u 0.1u 0.1u 9 ENCB 10 ENCG 11 ENCRC 16 VCRVIN 75 75 75
AK4707EQ
TVOUTL 32 TVOUTR 31 VCROUTL 30 VCROUTR 29 TST3 28 TVINL TVINR 23 TVSB 24 VCRINR 27 26
+ 10u + 10u + 10u + 10u
220k 220k 220k 220k 0.47u 0.47u 0.47u
300 300 300
Video 5V
controller
300 300 300
18 VCRRC
DACL DACR
MPEG decoder
22 VCRSB
17 VCRFB
12 ENCC 15 TVVIN 13 ENCV 14 ENCY
19 VCRG
VCRINL 25
20 VCRB
21 INT
Digital Ground
Analog Ground
Figure 17. Typical Connection Diagram (Single-ended Input )
MS0551-E-00 - 36 -
75
VCR SCART
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
encoder
VIDEO
75
75
75
75
75
75
75
0.47u
400
400
300
TV SCART
Micro
2006/10
ASAHI KASEI
[AK4707]
Grounding and Power Supply Decoupling
VD, VP, VVD1, VVD2, VSS and VVSS should be supplied from analog supply unit with low impedance and be separated from system digital supply. An electrolytic capacitor 10F parallel with a 0.1F ceramic capacitor should be attached to these pins to eliminate the effects of high frequency noise. The 0.1F ceramic capacitor should be placed as near to VD, VP, VVD1, VVD2 as possible.
Voltage Reference
Each DVCOM/PVCOM are signal ground of this chip. An electrolytic capacitor 10F parallel with a 0.1F ceramic capacitor should be attached to these VCOM pins to eliminate the effects of high frequency noise. No load current may be drawn from these VCOM pins. All signals, especially clocks, should be kept away from these VCOM pins in order to avoid unwanted coupling into the AK4707.
Analog Audio Outputs
The analog outputs are also single-ended and centered on 5.6V(typ.). The output signal range is typically 2Vrms. The DC voltage on analog outputs are eliminated by AC coupling.
MS0551-E-00 - 37 -
2006/10
ASAHI KASEI
[AK4707]
External Circuit Example
Analog Audio Input pin
300ohm TVINL/R VCRINL/R (Cable) 0.47F
Analog Audio Input pin
0.47F
AINR+ AINRAINL+ AINL-
Analog Audio Output pin
TVOUTL/R VCROUTL/R 10F 300ohm (Cable)
Total > 4.5kohm
Analog Video Input pin
ENCV, ENCY, VCRVIN, TVVIN, ENCRC, ENCC, VCRRC, ENCG, VCRG, ENCB, VCRB
75ohm
(Cable) 75ohm
0.1F
Analog Video Output pin
75ohm
TVVOUT, TVRC TVG, TVR, TVB, VCRVOUT max 15pF
(Cable) max 400pF 75ohm
MS0551-E-00 - 38 -
2006/10
ASAHI KASEI
[AK4707]
Slow Blanking pin
TVSB VCRSB 400ohm
(max 500ohm)
(Cable) max 3nF (with 400ohm) min: 10k ohm
Fast Blanking Input pin
VCRFB 75ohm (Cable) 75ohm
Fast Blanking Output pin
75ohm TVFB (Cable) 75ohm
MS0551-E-00 - 39 -
2006/10
ASAHI KASEI
[AK4707]
PACKAGE
48pin LQFP(Unit:mm)
9.0 0.2 7.0 36 37 25 24 9.0 0.2
1.70Max 0.13 0.13 1.40 0.05
48 1 0.5 0.22 0.08 12
13
7.0
0.145 0.05 0.10 M
0 10
0.10
0.5 0.2
Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate
MS0551-E-00 - 40 -
2006/10
ASAHI KASEI
[AK4707]
MARKING
AK4707EQ XXXXXXX
1
XXXXXXXX: Date code identifier
Revision History
Date (YY/MM/DD) 06/10/16 Revision 00 Reason First Edition Page Contents
MS0551-E-00 - 41 -
2006/10
ASAHI KASEI
[AK4707]
IMPORTANT NOTICE
* These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0551-E-00 - 42 -
2006/10

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